US 12,293,803 B2
Built-in self-test burst patterns based on architecture of memory
William Yu, Boise, ID (US); Daniele Balluchi, Cernusco Sul Naviglio (IT); Chad B. Erickson, Boise, ID (US); and Danilo Caraccio, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 13, 2022, as Appl. No. 17/943,706.
Prior Publication US 2024/0087664 A1, Mar. 14, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 29/10 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/10 (2013.01); G11C 29/1201 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device; and
a controller coupled to the memory device and comprising built-in self-test (BIST) circuitry comprising:
a first plurality of registers configured to store respective write burst patterns, wherein the write burst patterns are based, at least in part, on an architecture of the memory device; and
a second plurality of registers configured to store respective read burst patterns, wherein the read burst patterns are based, at least in part, on the architecture of the memory device; and
comparison circuitry configured to:
compare data read from the memory device with a selected one of the read burst patterns; and
provide an indication of whether the data read from the memory device corresponds to the selected one of the read burst patterns.