US 12,293,802 B2
Memory queue operations to increase throughput in an ATE system
Edmundo de la Puente, San Jose, CA (US); and Srdjan Malisic, San Jose, CA (US)
Assigned to Advantest Corporation, Tokyo (JP)
Filed by ADVANTEST CORPORATION, Tokyo (JP)
Filed on Aug. 3, 2023, as Appl. No. 18/229,981.
Claims priority of provisional application 63/407,099, filed on Sep. 15, 2022.
Claims priority of provisional application 63/440,610, filed on Jan. 23, 2023.
Prior Publication US 2024/0096432 A1, Mar. 21, 2024
Int. Cl. G11C 29/36 (2006.01); G11C 29/10 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 29/10 (2013.01); G11C 2029/3602 (2013.01)] 21 Claims
OG exemplary drawing
 
18. A method of testing a device under test (DUT) with a tester system, said method comprising:
using a microprocessor to automatically generate a plurality of test pattern vectors for application to said DUT;
filling a first-in-first-out (FIFO) buffer element at a first end with said test pattern vectors generated by said microprocessor, wherein a plurality of buffers of said FIFO buffer element are filled with data;
draining said FIFO buffer element at a second end using a direct memory access (DMA) engine wherein said draining is performed faster than said filling;
applying test pattern vectors drained from said FIFO buffer element to said DUT for testing thereof;
pausing generating of said test pattern vectors and pausing the filling of said FIFO buffer element upon said FIFO buffer element becoming full; and
pausing draining of said FIFO buffer element upon said FIFO buffer element becoming empty.