CPC G11C 29/12015 (2013.01) [G11C 7/222 (2013.01); G11C 8/18 (2013.01); H03K 5/1565 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a memory controller configured to provide a data strobe signal; and
a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller,
wherein the memory device includes:
a memory interface including a plurality of DQ driving circuits, the memory interface being configured to:
generate m phase clock signals based on the data strobe signal, where m is an integer equal to two or more,
determine a number n of the m phase clock signals to be provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, where n is an integer equal to 1 or more, and
provide the n phase clock signals to the plurality of DQ driving circuits.
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