US 12,293,801 B2
Memory interface and semiconductor memory device and semiconductor device including the same
Hojun Yoon, Suwon-si (KR); Youngdon Choi, Suwon-si (KR); Seungjin Park, Suwon-si (KR); Seunghoon Lee, Suwon-si (KR); and Junghwan Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 23, 2023, as Appl. No. 18/200,709.
Claims priority of application No. 10-2022-0154813 (KR), filed on Nov. 17, 2022.
Prior Publication US 2024/0170085 A1, May 23, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); H03K 5/156 (2006.01)
CPC G11C 29/12015 (2013.01) [G11C 7/222 (2013.01); G11C 8/18 (2013.01); H03K 5/1565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory controller configured to provide a data strobe signal; and
a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller,
wherein the memory device includes:
a memory interface including a plurality of DQ driving circuits, the memory interface being configured to:
generate m phase clock signals based on the data strobe signal, where m is an integer equal to two or more,
determine a number n of the m phase clock signals to be provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, where n is an integer equal to 1 or more, and
provide the n phase clock signals to the plurality of DQ driving circuits.