US 12,293,800 B2
Non-volatile memory with layout adaptive problematic word line detection
Xuan Tian, Shanghai (CN); Liang Li, Shanghai (CN); Dandan Yi, Shanghai (CN); Jojo Xing, Shanghai (CN); and Vincent Yin, Shanghai (CN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 3, 2023, as Appl. No. 18/346,367.
Claims priority of provisional application 63/510,716, filed on Jun. 28, 2023.
Prior Publication US 2025/0006287 A1, Jan. 2, 2025
Int. Cl. G11C 29/12 (2006.01); G11C 29/24 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 29/24 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory system, comprising:
a control circuit configured to connect to an array comprising a plurality of blocks, each block of the plurality of blocks comprising a plurality of non-volatile memory cells and a plurality of control lines for accessing the plurality of non-volatile memory cells, the plurality of control lines including word lines along which the plurality of non-volatile memory cells are connected, the control circuit including decoding circuitry comprising:
a first global supply line configured to provide bias voltages to a corresponding first control line of the plurality control of each block of the plurality of blocks;
a plurality of local supply lines for each block of the plurality of blocks;
a plurality of local supply line transfer switches configured to connect each of the local supply lines to a corresponding one of the corresponding block's plurality of control lines, including connecting a first local supply line to the first control line of the corresponding block of the plurality of blocks; and
a plurality of global supply line transfer switches, comprising a global supply line transfer switch corresponding to each of the plurality of local supply lines for each of the plurality of blocks, including a first global supply line transfer switch for each block of the plurality of blocks connecting the first global supply line to the corresponding first local supply line, where multiple ones of the plurality of local supply lines for each block of the plurality of blocks are routed over the global supply line transfer switches of each block of the plurality of blocks and include a first pair of the local supply lines routed adjacent to one another and adjacent to the first global supply line,
the control circuit configured to determine a short between the first pair of the local supply lines of one or more blocks of the plurality of blocks, where, to determine the short between the first pair of the local supply lines of the one or more of the plurality of blocks, the control circuit is configured to, while the plurality of local supply lines are disconnected to the corresponding ones of the corresponding block's plurality of control lines, concurrently:
bias, for each of the plurality of blocks, a first of the first pair of the local supply lines at a high voltage;
bias, for each of the plurality of blocks, a second of the first pair of the local supply lines at a low voltage; and
float the local supply lines other than those of the first pairs of the local supply lines.