US 12,293,799 B2
Memory circuit and method of operating same
Meng-Sheng Chang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,952.
Application 18/362,952 is a division of application No. 17/154,576, filed on Jan. 21, 2021, granted, now 11,791,005.
Claims priority of provisional application 63/034,133, filed on Jun. 3, 2020.
Prior Publication US 2023/0402117 A1, Dec. 14, 2023
Int. Cl. G11C 17/16 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 17/06 (2006.01); G11C 17/12 (2006.01)
CPC G11C 17/16 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 17/06 (2013.01); G11C 17/123 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a memory circuit, comprising
turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element, wherein the first fuse element is coupled between the first selection device and the first programming device;
turning off a second programming device and turning off a second selection device; and
blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device;
wherein the first fuse element is coupled in series with a first diode;
the first diode includes a first via;
a first connecting end of the first programming device is coupled to a first conductor in a first metal layer, and the first conductor is coupled to a second conductor in a second metal layer by a second via, the second metal layer being above the first metal layer; and
the first fuse element includes a third conductor in a third metal layer above the first metal layer and the second metal layer.