| CPC G11C 16/3459 (2013.01) [G11C 16/10 (2013.01)] | 20 Claims |

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1. An apparatus comprising:
a control circuit coupled to a plurality of non-volatile memory cells, the control circuit configured to:
perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops;
determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops;
determine a first voltage based on the first number of program loops;
add an adaptive voltage offset to the first voltage to obtain a second voltage; and
program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage,
wherein the adaptive voltage offset varies as a function of temperature.
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