US 12,293,794 B2
Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Oct. 2, 2023, as Appl. No. 18/375,869.
Application 17/579,364 is a division of application No. 16/901,758, filed on Jun. 15, 2020, granted, now 11,270,779, issued on Mar. 8, 2022.
Application 18/375,869 is a continuation of application No. 17/579,364, filed on Jan. 19, 2022, granted, now 11,817,156.
Application 16/901,758 is a continuation of application No. 15/820,337, filed on Nov. 21, 2017, granted, now 10,741,264, issued on Aug. 11, 2020.
Application 15/820,337 is a continuation of application No. 15/220,375, filed on Jul. 26, 2016, granted, now 9,892,800, issued on Feb. 13, 2018.
Claims priority of provisional application 62/235,322, filed on Sep. 30, 2015.
Prior Publication US 2024/0029803 A1, Jan. 25, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/28 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 88/00 (2025.01); H10B 43/10 (2023.01)
CPC G11C 16/3431 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0416 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/0491 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 30/0413 (2025.01); H10D 30/693 (2025.01); H10D 64/037 (2025.01); H10D 88/00 (2025.01); H10B 43/10 (2023.02)] 32 Claims
OG exemplary drawing
 
1. A memory structure formed above a semiconductor substrate, the semiconductor substrate having a substantially planar surface and having circuitry formed therein and thereon, the memory structure comprising:
an insulating layer over the semiconductor substrate;
a first stack of memory strings and a second stack of memory strings formed over the insulating layer and above the circuitry of the semiconductor substrate, wherein each stack of memory strings comprises two or more memory strings provided one on top of another and electrically isolated from each other, the memory strings being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface and wherein the first stack of memory strings and the second stack of memory strings being separated from each other a predetermined distance along a second direction transverse to the first direction and parallel to the planar surface;
a data storage material provided on sidewalls of the first and the second stacks of memory strings;
a plurality of local conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, wherein (a) the local conductors are arranged in a plurality of rows, each row of the local conductors extending along the first direction, with the local conductors within each row of the local conductors being electrically isolated from each other; (b) adjacent rows of the local conductors are separated from each other by either the first stack of memory strings or the second stack of memory strings; (c) each row of the local conductors is staggered relative to the local conductors of an adjacent neighboring row of the local conductors by virtue of each local conductor of each row not being aligned along the second direction to any local conductor in the adjacent neighboring row, but being staggered at least a predetermined distance along the first direction relative to the local conductors in the adjacent neighboring row; and (d) each local conductor is separated from one or both of the first stack memory strings and the second stack of memory strings by the data storage material;
first global conductive wiring having conductors each running along the second direction for connecting the local conductors to the circuitry;
wherein each memory string comprises a semiconductor layer provided between a first conductive layer and a second conductive layer, thereby providing a plurality of memory transistors, wherein the memory transistors of each memory string share the first conductive layer and the second conductive layer of the memory string as a common source region and a common drain region, respectively, and wherein each memory transistor further comprises a portion of the data storage material serving as a floating gate and one of the local conductors serving as a gate electrode.