| CPC G11C 16/26 (2013.01) [G11C 5/147 (2013.01); G11C 16/08 (2013.01); G11C 16/3431 (2013.01)] | 22 Claims |

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1. An apparatus comprising:
a plurality of memory cells;
a first storage storing a first adjustment table for adjusting a read voltage using a first offset level, the first adjustment table shared by both a first read operation and a second read operation; and
a second storage storing a second adjustment table for adjusting the read voltage using a second offset level, the second adjustment table being dedicated to the second read operation,
wherein, when a read retry operation is performed on the plurality of memory cells, the read voltage for the read retry operation is adjusted differently depending on whether the read retry operation is the first read operation or the second read operation.
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