| CPC G11C 16/24 (2013.01) [G11C 5/06 (2013.01); G11C 16/26 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
|
1. A memory device comprising:
a memory cell area including a first metal pad; and
a peripheral circuit area including a second metal pad and vertically connected to the memory cell area by the first metal pad and the second metal pad,
wherein the peripheral circuit area further includes:
a first substrate; and
a pass transistor circuit on the first substrate, the pass transistor circuit including a first pass transistor group, a second pass transistor group, and a third pass transistor group adjacently disposed in a first direction,
wherein the memory cell area further includes:
a second substrate;
a first memory block including a first plurality of channel structures;
a second memory block including a second plurality of channel structures, the second memory block being adjacent to the first memory block in the first direction;
a first plurality of word lines vertically stacked on the second substrate and connected to the first memory block; and
a second plurality of word lines vertically stacked on the second substrate and connected to the second memory block,
wherein one of the first pass transistor group, the second pass transistor group and the third pass transistor group includes:
a first pass transistor connected to a first word line among the first plurality of word lines, and
a second pass transistor connected to a second word line among the second plurality of word lines and adjacently disposed to the first pass transistor in a second direction, and
wherein the first and second word lines are disposed at a same level.
|