US 12,293,790 B2
Memory for programming data states of memory cells
Koichi Kawai, Yokohama (JP); Yoshihiko Kamata, Yokohama (JP); and Akira Goda, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,248.
Prior Publication US 2024/0071507 A1, Feb. 29, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 16/34 (2006.01); H03K 19/017 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 7/1048 (2013.01); G11C 16/3459 (2013.01); H03K 19/01742 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
apply a first voltage level indicative of a data state of a memory cell of the array of memory cells to a control gate of a transistor;
retain the first voltage level on the control gate of the transistor;
connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor; and
apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.