	US 12,293,789 B2
	Programming techniques for polarity-based memory cells
Innocenzo Tortorelli, Cernusco Sul Naviglio (IT); Mattia Boniardi, Cormano (IT); and Mattia Robustelli, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 14, 2024, as Appl. No. 18/664,199.
Application 18/664,199 is a continuation of application No. 17/885,131, filed on Aug. 10, 2022, granted, now 12,014,779.
Application 17/885,131 is a continuation of application No. 17/005,928, filed on Aug. 28, 2020, granted, now 11,423,988, issued on Aug. 23, 2022.
Prior Publication US 2024/0386963 A1, Nov. 21, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01)

CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 11/5607 (2013.01)]

20 Claims

1. A memory system, comprising:

one or more memory arrays; and

processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:

receive a command to write a set of memory cells within the one or more memory arrays to a first state; and

perform a write operation on the set of memory cells based at least in part on the command, wherein, to perform the write operation, the processing circuitry is configured to cause the memory system to:

apply a first pulse having a first polarity to the set of memory cells;

identify, based at least in part on applying the first pulse and within the set of memory cells, a subset of memory cells that are in a second state; and

apply, based at least in part on the identifying the subset of memory cells, a second pulse having a second polarity to the subset of memory cells to write the subset of memory cells to the first state.