US 12,293,787 B2
Memory system
Tokumasa Hara, Kawasaki (JP); and Noboru Shibata, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 3, 2023, as Appl. No. 18/364,524.
Application 18/364,524 is a continuation of application No. 17/582,330, filed on Jan. 24, 2022, granted, now 11,756,611.
Application 17/582,330 is a continuation of application No. 17/014,293, filed on Sep. 8, 2020, granted, now 11,264,090, issued on Mar. 1, 2022.
Claims priority of application No. 2019-166519 (JP), filed on Sep. 12, 2019; and application No. 2020-104833 (JP), filed on Jun. 17, 2020.
Prior Publication US 2023/0410899 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); H10B 69/00 (2023.01)
CPC G11C 11/56 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01); H10B 69/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region indicating an erased state for erasing data and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region and indicating a written state for writing data; and
a controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit and then cause the nonvolatile memory to execute a second program for writing data of the second bit, the third bit, and the fourth bit, wherein
the n-th threshold region has a higher voltage level than the (n−1)-th threshold region (n is a natural number of two or more and sixteen or less),
the controller is configured to cause the nonvolatile memory to execute the first program such that the threshold region in the memory cell is any threshold region of a seventeenth threshold region indicating an erased state for erasing data and an eighteenth threshold region having higher voltage levels than a voltage level of the seventeenth threshold region and indicating a written state for writing data according to the data of the first bit, and
the controller is configured to cause the nonvolatile memory to execute the second program such that the threshold region in the memory cell becomes any threshold region among the first to eighth threshold regions from the seventeenth threshold region or such that the threshold region becomes any threshold region among the ninth to sixteenth threshold regions from the eighteenth threshold region according to the data of the third bit and the fourth bit.