US 12,293,783 B2
Voltage management for improved tRP timing for FeRAM devices
Daniele Vimercati, El Dorado Hills, CA (US); and Giovanni Mazzeo, Sacramento, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 31, 2022, as Appl. No. 17/829,054.
Prior Publication US 2023/0410871 A1, Dec. 21, 2023
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2293 (2013.01) [G11C 11/221 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a command interface configured to receive read commands and write commands to invoke read and write operations;
a memory bank comprising a plurality of memory cells implemented using ferroelectric layers between plate lines and digit lines; and
bank control circuitry configured to control operation of the memory bank, wherein the operation of the memory bank comprises programming both high and low logic values as a write back to the plurality of memory cells during a read and write phase where the read and write operations are performed after sensing values from the plurality of memory cells, wherein a plate voltage of a plate line of the plate lines is maintained at a constant voltage from the sensing through programming both the high and low logic values in a same period with a constant voltage of a wordline by swinging the digit lines alternatingly between a maximum voltage and a minimum voltage during the same period, wherein the constant voltage is between the maximum voltage and the minimum voltage of the digit lines during the programming of the high and low logic values.