US 12,293,782 B2
Convertible memory device
Gyeong Cheol Park, Gyeonggi-do (KR); and Min Chul Sung, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 21, 2023, as Appl. No. 18/186,960.
Claims priority of application No. 10-2022-0141163 (KR), filed on Oct. 28, 2022.
Prior Publication US 2024/0144987 A1, May 2, 2024
Int. Cl. G11C 7/02 (2006.01); G11C 11/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4078 (2006.01); G11C 11/4091 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2259 (2013.01); G11C 11/2295 (2013.01); G11C 11/2297 (2013.01); G11C 11/4076 (2013.01); G11C 11/4078 (2013.01); G11C 11/4091 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including:
a first operational circuit configured to perform a first operation according to a first sensing control signal; and
a second operational circuit configured to perform a second operation according to a second sensing control signal; and
an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property based on at least any of numbers of accesses to the respective memory cells in each of the first operation and the second operation, and a consistent value status of data stored in at least a part of the memory cells in each of the first operation and the second operation.