US 12,293,735 B2
Driving method of liquid crystal display panel and liquid crystal display panel
Zuwei Weng, Beijing (CN); Yichiang Lai, Beijing (CN); and Bo Hu, Beijing (CN)
Assigned to FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Fujian (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/577,838
Filed by FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Fuzhou (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Aug. 25, 2022, PCT No. PCT/CN2022/114839
§ 371(c)(1), (2) Date Jan. 9, 2024,
PCT Pub. No. WO2024/040523, PCT Pub. Date Feb. 29, 2024.
Prior Publication US 2025/0006150 A1, Jan. 2, 2025
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3614 (2013.01) [G09G 3/3688 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0257 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A driving method of a liquid crystal display panel, wherein the liquid crystal display panel comprises a pixel array, the pixel array comprises a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels, the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns, each of the plurality of gate lines provides a gate signal for at least one row of sub-pixels, each of the plurality of data lines provides a data signal for at least one column of sub-pixels, each sub-pixel is connected with a corresponding gate line and a corresponding data line, and
the driving method comprises:
providing a first gate signal to a first gate line corresponding to a first row of sub-pixels among the plurality of rows of sub-pixels, wherein the first gate signal comprises an on period and an off period used to control the first row of sub-pixels to be turned on and off respectively;
writing, during the on period of the first gate signal, a plurality of first data signals to sub-pixels among the first row of sub-pixels through the plurality of data lines, wherein the plurality of first data signals comprise a positive polarity data signal and a negative polarity data signal, and
during the on period of the first gate signal, a first writing time length of the negative polarity data signal is less than a second writing time length of the positive polarity data signal;
wherein a delay time of the negative polarity data signal relative to a starting time point of the on period corresponding to the first gate signal is a first time length,
a delay time of the positive polarity data signal relative to the starting time point of the on period corresponding to the first gate signal is a second time length, and
the first time length is greater than the second time length, so that the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal during the on period of the first gate signal.