US 12,293,722 B2
Shift register having scan cicuit and reset circuit, scan driving circuit and display substrate
Huijuan Yang, Beijing (CN); Maoying Liao, Beijing (CN); Bo Zhang, Beijing (CN); Xiaoqing Shu, Beijing (CN); Liheng Wei, Beijing (CN); and Lingtong Li, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/925,696
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Dec. 21, 2021, PCT No. PCT/CN2021/140079
§ 371(c)(1), (2) Date Nov. 16, 2022,
PCT Pub. No. WO2023/115331, PCT Pub. Date Jun. 29, 2023.
Prior Publication US 2024/0221675 A1, Jul. 4, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/32 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G11C 19/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register, configured to be applied to a display substrate including a plurality of rows of sub-pixels;
the shift register being electrically connected to a single row of sub-pixels in the plurality of rows of sub-pixels, and being further configured to transmit a scan signal and a reset signal to the single row of sub-pixels; wherein
the shift register comprises:
a scan circuit electrically connected to a first input signal terminal, a first clock signal terminal, a second clock signal terminal, a first voltage signal terminal and a second voltage signal terminal; the scan circuit being configured to output the scan signal due to cooperation of a first input signal transmitted by the first input signal terminal, a first clock signal transmitted by the first clock signal terminal, a second clock signal transmitted by the second clock signal terminal, a first voltage signal transmitted by the first voltage signal terminal and a second voltage signal transmitted by the second voltage signal terminal; and
a reset circuit electrically connected to a second input signal terminal, a third clock signal terminal, a fourth clock signal terminal, a third voltage signal terminal and a fourth voltage signal terminal; the reset circuit being configured to output the reset signal due to cooperation of a second input signal transmitted by the second input signal terminal, a third clock signal transmitted by the third clock signal terminal, a fourth clock signal transmitted by the fourth clock signal terminal, a third voltage signal transmitted by the third voltage signal terminal and a fourth voltage signal transmitted by the fourth voltage signal terminal;
wherein the scan circuit and the reset circuit are configured to output signals independently from each other;
the scan circuit includes a first output transistor; a first electrode of the first output transistor is electrically connected to the second voltage signal terminal, and a second electrode of the first output transistor is electrically connected to a scan signal output terminal; and
the reset circuit includes a second output transistor; a first electrode of the second output transistor is electrically connected to the fourth voltage signal terminal, and a second electrode of the second output transistor is electrically connected to a reset signal output terminal;
wherein a channel width of the first output transistor is greater than or equal to a channel width of the second output transistor; or
a channel width of the first output transistor is greater than or equal to a channel width of the second output transistor, and a ratio of the channel width of the first output transistor to the channel width of the second output transistor is in a range from 1:1 to 20:1, inclusive.