US 12,293,719 B2
Shift register, driving circuit and display substrate
Yunsheng Xiao, Beijing (CN); and Haigang Qing, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Mar. 15, 2024, as Appl. No. 18/607,059.
Application 18/607,059 is a division of application No. 17/763,758, granted, now 11,967,278, previously published as PCT/CN2021/079682, filed on Mar. 9, 2021.
Prior Publication US 2024/0221668 A1, Jul. 4, 2024
Int. Cl. G09G 3/00 (2006.01); G09G 3/20 (2006.01); G09G 3/32 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A shift register, comprising:
a first transistor having a control electrode coupled to a first clock signal line to receive a first clock signal, a first electrode coupled to a signal input terminal, and a second electrode coupled to a first node;
a second transistor having a control electrode coupled to the first node, a first electrode coupled to a second node, and a second electrode coupled to the first clock signal line to receive the first clock signal;
a third transistor having a control electrode coupled to the first clock signal line to receive the first clock signal, a first electrode coupled to a first power terminal, and a second electrode coupled to the second node;
a fourth transistor having a control electrode coupled to a second clock signal line to receive a second clock signal, a first electrode coupled to a second electrode of a fifth transistor, and a second electrode coupled to the first node;
the fifth transistor having a control electrode coupled to a third node and a first electrode coupled to a second power terminal;
a first capacitor having a first electrode coupled to a fourth node and a second electrode coupled to the second clock signal line, the first node being coupled to the fourth node;
an impedance transistor having a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node;
a first output control circuit coupled to the third node, the fourth node and a first signal output terminal, and configured to output a first driving signal to the first signal output terminal in response to the control of signals at the third node and the fourth node; and
a second output control circuit coupled to at least the first signal output terminal and a second signal output terminal, and configured to output a second driving signal with a phase opposite to that of the first driving signal, to the second signal output terminal, according to the first driving signal output from the first signal output terminal,
wherein the second output control circuit comprises:
an eleventh transistor having a control electrode coupled to the fifth node, a first electrode coupled to the first power terminal, and a second electrode coupled to a seventh node;
a twelfth transistor having a control electrode coupled to the first signal output terminal, a first electrode coupled to the seventh node, and a second electrode coupled to the second power terminal;
a fourth capacitor having a first electrode coupled to the first clock signal line and a second electrode coupled to the seventh node;
a fourteenth transistor having a control electrode coupled to the seventh node, a first electrode coupled to the first power terminal, and a second electrode coupled to the second signal output terminal; and
a fifteenth transistor having a control electrode coupled to the first signal output terminal, a first electrode coupled to the second signal output terminal, and a second electrode coupled to the second power terminal.