| CPC G09G 3/3233 (2013.01) [H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01)] | 16 Claims |
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1. A pixel drive circuit, comprising:
a light-emitting device between and electrically connected to a first power supply terminal and a second power supply terminal;
a drive transistor having a gate electrically connected to a first node and a source and a drain between and electrically connected to a second node and a third node, wherein the drive transistor is configured to generate a driving current to drive the light-emitting device during a light-emitting stage to emit light in response to a data signal written in a data write stage;
a first light-emitting control transistor having a source and a drain between and electrically connected to the first power supply terminal and the second node, and a gate configured to receive a first light-emitting control signal;
a second light-emitting control transistor having a source and a drain between and electrically connected to the third node and the light-emitting device, and a gate configured to receive a second light-emitting control signal;
a data transistor, wherein one of a source and a drain of the data transistor is directly electrically connected to the second node, the other of the source and the drain of the data transistor is configured to receive the data signal, a gate of the data transistor is configured to receive a first scan signal;
a compensation transistor having a source and a drain between and directly electrically connected to the first node and the third node, and a gate configured to receive a second scan signal;
a first reset transistor, wherein one of a source and a drain of the first reset transistor is electrically connected to the first node, the other of the source and the drain of the first reset transistor is configured to receive a first reset signal, and a gate of the first reset transistor is configured to receive a third scan signal; and
a second reset transistor, wherein one of a source and a drain of the second reset transistor is electrically connected to the light-emitting device, the other of the source and the drain of the second reset transistor is configured to receive a second reset signal different from the first reset signal, and a gate of the second reset transistor is configured to receive a fourth scan signal;
wherein the first light-emitting control transistor is configured to transmit a first voltage signal supplied from the first power supply terminal to the second node and the third node at a node setting stage after the data write stage and before the light-emitting stage.
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