| CPC G09G 3/3233 (2013.01) [H10K 59/1213 (2023.02); H10K 59/131 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01); G09G 2320/0233 (2013.01)] | 20 Claims |

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1. A display substrate, comprising:
a substrate comprising a display region and a non-display region, wherein the display region is surrounded by at least part of the non-display region;
a plurality of light-emitting elements disposed in the display region;
a plurality of pixel circuit groups disposed in the display region, at least one of the pixel circuit groups comprising a plurality of pixel circuit subgroups arranged in a first direction, each of the plurality of pixel circuit subgroups comprising a plurality of pixel circuits arranged in a second direction, and the first direction intersecting the second direction;
a plurality of first scanning lines and a plurality of data signal lines disposed in the display region and the non-display region and coupled to the plurality of pixel circuit subgroups in the plurality of pixel circuit groups; and
a plurality of switching control lines and a plurality of data lines disposed in the non-display region and coupled to the plurality of pixel circuit subgroups in the plurality of pixel circuit groups;
wherein at least one of the pixel circuits comprises a data writing circuit and a drive circuit; the data writing circuit being coupled to the first scanning line, the switching control line, the data signal line, and the drive circuit, and the data writing circuit being configured to control, in response to a first scanning signal provided by the first scanning line and a switching control signal provided by the switching control line, connection and disconnection between the data signal line and the drive circuit; the drive circuit being further coupled to the light-emitting element, and the drive circuit being configured to drive the light-emitting element to emit light in response to a data signal provided by the data writing circuit; and
the pixel circuits comprised in the same pixel circuit subgroup being coupled to the same switching control line, and the pixel circuits comprised in the same pixel circuit subgroup being coupled to the same data signal line; the plurality of pixel circuit subgroups in the same pixel circuit group being coupled to different switching control lines, and the plurality of data signal lines coupled to the plurality of pixel circuit subgroups in the same pixel circuit group being coupled to the same data line, wherein the plurality of data signal lines are configured to receive a data signal from the data line.
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