	US 12,293,709 B2
	Pixel circuit and driving method for same, display panel, and display apparatus
Mengmeng Zhang, Wuhan (CN); and Jing Huang, Shanghai (CN)
Assigned to WUHAN TIANMA MICROELECTRONICS CO., LTD., Wuhan (CN); and WUHAN TIANMA MICROELECTRONICS CO., LTD. Shanghai Branch, Shanghai (CN)
Filed by WUHAN TIANMA MICROELECTRONICS CO., LTD., Wuhan (CN); and Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai (CN)
Filed on Mar. 11, 2022, as Appl. No. 17/692,664.
Claims priority of application No. 202111431600.X (CN), filed on Nov. 29, 2021.
Prior Publication US 2022/0199024 A1, Jun. 23, 2022
Int. Cl. G09G 3/3233 (2016.01)

CPC G09G 3/3233 (2013.01) [G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01); G09G 2320/0247 (2013.01)]

6 Claims

1. A pixel circuit, comprising:

a driving transistor, a gate of the driving transistor being electrically connected to a first node, a first electrode of the driving transistor being electrically connected to a second node, and a second electrode of the driving transistor being electrically connected to a third node;

at least one control circuit that is electrically connected to the first node and configured to write a voltage into the first node, each of the at least one control circuit comprising a first sub-circuit and a second sub-circuit connected in series, and an intermediate node being disposed between the first sub-circuit and the second sub-circuit; and

a voltage regulation circuit that is electrically connected to the intermediate node of the at least one control circuit;

wherein a driving cycle of the pixel circuit comprises a writing frame and at least one holding frame, the writing frame comprises a first non-light-emission period, the at least one holding frame comprises a second non-light-emission period, and the voltage regulation circuit is configured to adjust, in the second non-light-emission period of at least one of the at least one holding frames, a voltage of the intermediate node electrically connected to the voltage regulation circuit to a first voltage, wherein |V−V_N1|<ΔV, V represents the first voltage, V_N1represents the voltage of the first node, and ΔV represents a voltage difference;

the at least one control circuit comprises:

a first reset circuit, electrically connected between a reset signal line and the first node, the first reset circuit comprising a first reset sub-circuit and a second reset sub-circuit connected in series, wherein a first intermediate node is disposed between the first reset sub-circuit and the second reset sub-circuit; and

a threshold compensation circuit, electrically connected between the third node and the first node, the threshold compensation circuit comprising a first compensation sub-circuit and a second compensation sub-circuit connected in series, wherein a second intermediate node is disposed between the first compensation sub-circuit and the second compensation sub-circuit;

wherein the voltage regulation circuit is electrically connected to at least one of the first intermediate node or the second intermediate node; and

the voltage regulation circuit comprises a capacitance regulation sub-circuit, a first terminal of the capacitance regulation sub-circuit receives a first signal, and a second terminal of the capacitance regulation sub-circuit is electrically connected to the at least one of the first intermediate node or the second intermediate node; and

in the second non-light-emission period of at least one of the at least one holding frame, the first signal jumps between an enable level and a non-enable level, and the capacitance regulation sub-circuit is configured to adjust, by using a jump of the first signal, a voltage of the at least one of the first intermediate node or the second intermediate node electrically connected to the capacitance regulation sub-circuit to the first voltage;

the capacitance regulation sub-circuit comprises a regulation capacitor, a first electrode of the regulation capacitor receives the first signal, and a second electrode of the regulation capacitor is electrically connected to the at least one of the first intermediate node or the second intermediate node;

the pixel circuit further comprises:

a light-emitting control circuit, comprising a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, wherein the first light-emitting control sub-circuit is electrically connected to a first light-emitting control signal line, a power signal line, and the second node respectively, and the first light-emitting control sub-circuit is configured to write a power voltage into the second node in response to an enable level of a first light-emitting control signal; and wherein the second light-emitting control sub-circuit is electrically connected to a second light-emitting control signal line, the third node, and an anode of a light-emitting diode respectively, and the second light-emitting control sub-circuit is configured to write a voltage of the third node into the anode of the light-emitting diode in response to an enable level of a second light-emitting control signal; and

a second reset circuit, electrically connected to a fourth scanning signal line, the reset signal line, and the anode of the light-emitting diode respectively, wherein the second reset circuit is configured to write a reset voltage into the anode of the light-emitting diode in response to an enable level of a fourth scanning signal;

wherein the first compensation sub-circuit is electrically connected to the fourth scanning signal line and configured to write a voltage of the second node into the second intermediate node in response to the enable level of the fourth scanning signal;

wherein the second compensation sub-circuit is electrically connected to a third scanning signal line and configured to write a voltage of the second intermediate node into the first node in response to the enable level of a third scanning signal;

wherein the first electrode of the regulation capacitor is electrically connected to the fourth scanning signal line, and the second electrode of the regulation capacitor is electrically connected to the second intermediate node, or the second electrode of the regulation capacitor is electrically connected to both the first intermediate node and the second intermediate node;

wherein the first non-light-emission period and the second non-light-emission period each comprise a first sub-period and a second sub-period, and the first sub-period is prior to the second sub-period; in the first sub-period, the first light-emitting control signal has a non-enable level, the second light-emitting control signal has an enable level; and in the second sub-period, the first light-emitting control signal and the second light-emitting control signal each have a non-enable level; and

wherein the fourth scanning signal comprises an active level set that is outputted periodically, the active level set comprises a first enable level and a second enable level, the first enable level is in the first sub-period, and the second enable level is in the second sub-period and overlaps with an enable level of the third scanning signal;

in the first sub-period of the second non-light emission period of the holding frame, the second reset circuit and the first compensation sub-circuit are turned on by the fourth scanning signal line, and the second light-emitting control sub-circuit is turned on through the second light-emitting control signal line, thereby causing a path between the reset signal line and the second intermediate node and the first intermediate node to be conductive, and the second compensation sub-circuit connected to the third scanning signal line to be non-conductive, thereby writing a reset signal to at least one of the first intermediate node and the second intermediate node;

in such a configuration, the reset voltage is written into the at least one of the first intermediate node and the second intermediate node, and then a potential of at least one of the first intermediate node and the second intermediate node is raised to a first voltage based on the reset voltage;

during the first sub-period of the second non-light-emission period of the holding frame, the fourth scanning signal has the first enable level, the second light-emitting control signal has an enable level, at which time the reset voltage is further written into the second intermediate node via the second compensation sub-circuit, and at which time the first light-emitting control signal has a non-enable level such that a pathway between the power signal line and the second node is disconnected;

during the second sub-period of the second non-light-emission period of the holding frame, the fourth scanning signal has the second enable level, and the second enable level overlaps with a non-enable level of the first light-emitting control signal emit and a non-enable level of the first light-emitting control signal emit.