| CPC G09G 3/32 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01)] | 19 Claims |
|
1. A pixel circuit comprising:
a first transistor configured to provide a data signal to a first node according to a scan signal;
a second transistor configured to initialize the first node;
a first capacitor configured to be coupled between one terminal to which a light emission signal is provided and the first node;
a second capacitor configured to be coupled between the first node and a second node;
a third transistor configured to include a gate coupled to the second node and one terminal coupled to a third node;
a fourth transistor configured to include a gate coupled to the second node and one terminal coupled to the third node;
a fifth transistor configured to be coupled between the second node and the third node;
a drive transistor configured to include a gate to which a voltage corresponding to the voltage at the third node is supplied; and
a micro light emitting diode configured to be coupled to the drive transistor,
wherein the third transistor is a low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT), and the fourth transistor is an oxide TFT.
|