| CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0267 (2013.01)] | 21 Claims |
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1. A scan driving circuit comprising a plurality of stages, each of the plurality of stages comprising:
a buffer part which is electrically connected to an output terminal and operates in response to a potential of a first control node;
a holding part which is electrically connected to the output terminal and operates in response to a potential of a second control node; and
an inverter part which is electrically connected to the first and second control nodes and controls the potentials of the first and second control nodes, wherein
the inverter part comprises: a control transistor including:
a gate electrically connected to the first control node; and
a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage, and
the control transistor further includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.
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