| CPC G09G 3/32 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/045 (2013.01)] | 16 Claims |

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1. A pixel compensation circuit, comprising:
a drive transistor having a gate connected to a first node, a drain connected to a first power supply terminal, and a source connected to a second node;
a data write module connected to a first control signal line, a data line, and the first node, and transmitting a data signal transmitted by the data line to the first node in response to a first control signal transmitted by the first control signal line;
a first initialization module connected to a second control signal line, a first wiring, and the second node, and transmitting a first initialization signal transmitted by the first wiring to the second node in response to a second control signal transmitted by the second control signal line;
a second initialization module connected to a third control signal line, a second wiring, and the first node, and transmitting a second initialization signal transmitted by the second wiring to the first node in response to a third control signal transmitted by the third control signal line;
a storage capacitor having two plates connected to the first node and the second node, respectively; and
a light-emitting device, wherein one terminal of the light-emitting device is connected to the first power supply terminal, and the other terminal of the light-emitting device is connected to the second power supply terminal;
wherein drive timing of the pixel compensation circuit comprises a threshold voltage compensation stage in which a detected threshold voltage of the drive transistor is less than an actual threshold voltage of the drive transistor, and
wherein the detected threshold voltage of the drive transistor is determined by a pulse width of the third control signal during the threshold voltage detection stage.
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