| CPC G09G 3/32 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
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1. A scan driver, comprising:
a plurality of stages each including:
a first node control circuit, which controls a voltage of a first node in response to an input signal, a first clock signal, and a second clock signal;
an inverted carry node control circuit, which controls a voltage of an inverted carry node in response to the voltage of the first node;
a carry output circuit, which outputs a carry signal in response to the voltage of the inverted carry node;
a fourth node control circuit, which controls a voltage of a fourth node in response to the carry signal;
a second node control circuit, which controls a voltage of a second node in response to the carry signal, an enable signal, and the voltage of the inverted carry node;
a third node control circuit, which controls a voltage of a third node in response to the voltage of the second node and the voltage of the fourth node; and
a scan output circuit, which outputs a scan signal in response to the voltage of the third node and the voltage of the fourth node.
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