US 12,293,695 B2
Driver and display device
Kyonghwan Oh, Yongin-si (KR); Taehoon Kwon, Yongin-si (KR); Mina Kim, Yongin-si (KR); and Kyung-Hoon Kim, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Jan. 3, 2024, as Appl. No. 18/403,346.
Claims priority of application No. 10-2023-0062886 (KR), filed on May 16, 2023.
Prior Publication US 2024/0386838 A1, Nov. 21, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2096 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A driver disposed in a display panel, the driver including:
a plurality of stages, at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal based on a voltage of the first node, at least one of the inverters including:
a p-type metal-oxide-semiconductor transistor including a first active region; and
an n-type metal-oxide-semiconductor transistor including a second active region,
wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage, and
the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor.
 
31. A driver disposed in a display panel, the driver including:
a plurality of stages, at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal based on a voltage of the first node, at least one of the inverters includes:
a p-type metal-oxide-semiconductor transistor; and
an n-type metal-oxide-semiconductor transistor including:
an active region;
a top gate disposed above the active region; and
a bottom gate disposed below the active region,
wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage.
 
35. A display device comprising:
a display panel including a plurality of pixels;
a data driver which provides data signals to the plurality of pixels;
a gate driver which provides gate signals to the plurality of pixels;
an emission driver which provides emission signals to the plurality of pixels; and
a controller which controls the data driver, the gate driver and the emission driver,
wherein at least one of the gate driver and the emission driver includes a plurality of stages, and
wherein at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal corresponding to one of the gate signals or one of the emission signals based on a voltage of the first node,
wherein at least one of the inverters includes a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage, and
wherein a first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of a second active region of the n-type metal-oxide-semiconductor transistor.