US 12,293,462 B2
Tile sequencing mechanism
Subramaniam Maiyuran, Gold River, CA (US); Saurabh Sharma, El Dorado Hills, CA (US); Jorge F. Garcia Pabon, Folsom, CA (US); Raghavendra Kamath Miyar, Bangalore (IN); Sudheendra Srivathsa, Bangalore (IN); Justin Decell, San Francisco, CA (US); and Aditya Navale, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 10, 2024, as Appl. No. 18/409,753.
Application 18/409,753 is a continuation of application No. 17/590,521, filed on Feb. 1, 2022, granted, now 11,900,539.
Application 17/590,521 is a continuation of application No. 16/914,783, filed on Jun. 29, 2020, granted, now 11,250,627, issued on Feb. 15, 2022.
Prior Publication US 2024/0185527 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/10 (2011.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 17/20 (2006.01)
CPC G06T 17/20 (2013.01) [G06T 1/20 (2013.01); G06T 15/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processing unit (GPU), comprising:
a cache memory to store object data and associated control data for objects to be rendered via tile-based rendering;
sequencer circuitry to generate a plurality of batches of objects to be rendered, determine tiles intersected by objects in each of the plurality of batches, and select, based on the tiles intersected by objects, a cache aware tile walk pattern; and
rasterization circuitry to walk lit tiles according to the cache aware tile walk pattern and process primitive commands for objects in the plurality of batches of objects that are associated with the tiles intersected by the objects.