US 12,293,282 B2
Optoelectronic computing systems
Yichen Shen, Hangzhou (CN); Huaiyu Meng, Medford, MA (US); Li Jing, Cambridge, MA (US); Rumen Dangovski, Cambridge, MA (US); Peng Xie, Dublin, CA (US); Matthew Khoury, Cambridge, MA (US); Cheng-Kuan Lu, Littleton, MA (US); Ronald Gagnon, North Grafton, MA (US); Maurice Steinman, Marlborough, MA (US); Jianhua Wu, Quincy, MA (US); and Arash Hosseinzadeh, Andover, MA (US)
Assigned to Lightelligence PTE. Ltd., Singapore (SG)
Filed by Lightelligence PTE. Ltd., Singapore (SG)
Filed on Mar. 20, 2024, as Appl. No. 18/610,442.
Application 18/610,442 is a continuation of application No. 18/221,068, filed on Jul. 12, 2023, granted, now 12,073,315.
Application 18/221,068 is a continuation of application No. 16/431,167, filed on Jun. 4, 2019, granted, now 11,734,555, issued on Aug. 22, 2023.
Claims priority of provisional application 62/820,562, filed on Mar. 19, 2019.
Claims priority of provisional application 62/792,144, filed on Jan. 14, 2019.
Claims priority of provisional application 62/744,706, filed on Oct. 12, 2018.
Claims priority of provisional application 62/680,944, filed on Jun. 5, 2018.
Prior Publication US 2024/0232604 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06E 1/04 (2006.01); G02F 1/00 (2006.01); G02F 3/02 (2006.01); G06E 3/00 (2006.01); G06F 17/14 (2006.01); G06F 17/16 (2006.01); G06N 3/067 (2006.01); G06N 3/08 (2023.01); G02F 1/225 (2006.01)
CPC G06N 3/0675 (2013.01) [G02F 1/00 (2013.01); G02F 3/024 (2013.01); G06E 1/045 (2013.01); G06E 3/005 (2013.01); G06E 3/006 (2013.01); G06E 3/008 (2013.01); G06F 17/14 (2013.01); G06F 17/16 (2013.01); G06N 3/08 (2013.01); G02F 1/225 (2013.01)] 56 Claims
OG exemplary drawing
 
1. A system, comprising:
a first unit comprising electronic circuitry;
a controller comprising integrated circuitry configured to perform operations comprising:
receiving a computation request comprising an input dataset that comprises a first digital input vector or matrix; and
generating, through the first unit, a first plurality of modulator control signals based on the first digital input vector or matrix;
a processor unit comprising:
a plurality of optical modulators coupled to a light source and the first unit, the plurality of optical modulators being configured to generate an optical input vector or matrix by modulating a plurality of light outputs provided by the light source based on the first plurality of modulator control signals, the optical input vector or matrix comprising a plurality of modulated optical signals; and
a matrix multiplication unit coupled to the plurality of optical modulators, the matrix multiplication unit being configured to transform the optical input vector or matrix into an analog output vector or matrix based on a plurality of weights configured in the matrix multiplication unit; and
a second unit comprising electronic circuitry coupled to the matrix multiplication unit and configured to convert the analog output vector or matrix into a digitized output vector or matrix.