US 12,293,257 B2
Device with two superposed electrostatic control gate levels
Benoit Bertrand, Grenoble (FR); Biel Martinez I Diaz, Grenoble (FR); Yann-Michel Niquet, Grenoble (FR); and Maud Vinet, Grenoble (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Mar. 9, 2022, as Appl. No. 17/654,181.
Claims priority of application No. 2102536 (FR), filed on Mar. 15, 2021.
Prior Publication US 2022/0292384 A1, Sep. 15, 2022
Int. Cl. G06N 10/40 (2022.01)
CPC G06N 10/40 (2022.01) 17 Claims
OG exemplary drawing
 
1. A quantum device, comprising:
a semiconductor portion comprising several first regions configured to form quantum dots of at least one spin qubit of the quantum device, each disposed between at least two second regions forming tunnel barriers and juxtaposed with the two second regions;
first electrostatic control gates, each comprising at least a first portion of electrically conductive material; and
second electrostatic control gates, each second electrostatic control gate being arranged on a first electrostatic control gate, of the first electrostatic control gates, and each second electrostatic control gate comprising at least a second portion of electrically conductive material and at least a second gate dielectric disposed between the second portion of electrically conductive material and the first portion of electrically conductive material of one of the first electrostatic control gates, such that each of the first electrostatic control gates is disposed between the semi-conductor portion and one of the second electrostatic control gates,
wherein the second electrostatic control gates are solely located in a vertical extension of the first electrostatic control gates, said vertical extension being perpendicular to a main plane of the semiconductor portion, and
wherein, in a first configuration, the first and second electrostatic control gates are disposed above the first regions of the semiconductor portion, or wherein, in a second configuration, the first and second electrostatic control gates are disposed above the second regions of the semiconductor portion.