US 12,293,237 B2
Systems, methods and devices for determining work placement on processor cores
Guy M. Therien, Sherwood, OR (US); Michael D. Powell, Northborough, MA (US); Venkatesh Ramani, Milpitas, CA (US); Arijit Biswas, Northborough, MA (US); and Guy G. Sotomayor, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 19, 2023, as Appl. No. 18/545,912.
Application 18/545,912 is a continuation of application No. 17/857,394, filed on Jul. 5, 2022, granted, now 11,853,809.
Application 17/857,394 is a continuation of application No. 17/173,100, filed on Feb. 10, 2021, granted, now 11,409,577, issued on Aug. 9, 2022.
Application 17/173,100 is a continuation of application No. 16/107,691, filed on Aug. 21, 2018, granted, now 10,922,143, issued on Feb. 16, 2021.
Application 16/107,691 is a continuation of application No. 14/997,032, filed on Jan. 15, 2016, granted, now 10,073,718, issued on Aug. 23, 2018.
Prior Publication US 2024/0118942 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 1/324 (2019.01); G06F 1/329 (2019.01); G06F 1/3296 (2019.01); G06F 9/30 (2018.01)
CPC G06F 9/5083 (2013.01) [G06F 1/324 (2013.01); G06F 1/329 (2013.01); G06F 1/3296 (2013.01); G06F 9/3009 (2013.01); G06F 9/5033 (2013.01); G06F 9/5044 (2013.01); G06F 9/5094 (2013.01); Y02D 10/00 (2018.01)] 18 Claims
OG exemplary drawing
 
1. A processor, comprising:
a plurality of cores that are architecturally identical;
circuitry to store data indicating physical characteristics of each core of the plurality of cores, the physical characteristics including a maximum frequency of each core of the plurality of cores, at least one core of the plurality of cores having different physical characteristics than another core of the plurality of cores; and
power control circuitry to control frequencies and voltages of the plurality of cores in accordance with corresponding per-core performance values, the power control circuitry including an interface to receive performance requests from system software and to provide information related to the per-core performance values to the system software;
execution circuitry to execute instructions of a driver to determine the per-core performance values,
wherein when a first operational mode is enabled, the execution circuitry is to:
determine a first ranking of the plurality of cores based on the physical characteristics of the plurality of cores, and
provide the first ranking to the system software, and
wherein when the first operational mode is not enabled, the execution circuitry is to:
determine a second ranking of the plurality of cores based on the physical characteristics of the plurality of cores, the second ranking different from the first ranking, and
provide the second ranking to the system software.