US 12,293,192 B2
Bundling and dynamic allocation of register blocks for vector instructions
Bradley Gene Burgess, Sunset Valley, TX (US); David Kravitz, Cambridge, MA (US); and Alexandre Solomatnikov, San Carlos, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Apr. 28, 2023, as Appl. No. 18/140,792.
Prior Publication US 2024/0362025 A1, Oct. 31, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30123 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a decoder to:
decode a vector instruction into micro-operations; and
bundle micro-operations into bundled micro-operations, wherein:
the vector instruction is associated with a length multiplier;
the length multiplier is at least two; and
a number of the bundled micro-operations is less than the length multiplier; and
an issue queue to:
allocate an issue queue entry to each of the bundled micro-operations; and
execute each of the bundled micro-operations a number of times from the issue queue entry, wherein the number of times multiplied by the number of the bundled micro-operations is equal to the length multiplier.