| CPC G06F 9/3836 (2013.01) [G06F 9/30076 (2013.01); G06F 9/30087 (2013.01); G06F 9/3854 (2023.08); G06F 2212/683 (2013.01)] | 20 Claims |
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1. An integrated circuit comprising:
at least a first processor core executing instructions in a pipeline configured for out-of-order issuing of instructions; and
instruction management circuitry configured for managing external instructions received from outside the first processor core, the managing including:
updating issue status information for a plurality of instructions stored in an instruction queue,
maintaining an indication of a program order for the plurality of instructions as they are stored in the instruction queue,
processing at least a portion of the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, wherein the first queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with no later instructions in the program order having been issued, and the second queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with all earlier instructions in the program order having been issued, and
inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
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