US 12,293,188 B2
Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm
Morris Jacob Creeger, Santa Clara, CA (US); Tianfang Liu, Santa Clara, CA (US); Frederick Furtek, Santa Clara, CA (US); and Paul L. Master, Santa Clara, CA (US)
Assigned to Cornami, Inc., Santa Clara, CA (US)
Filed by Cornami, Inc., Santa Clara, CA (US)
Filed on Jul. 8, 2022, as Appl. No. 17/860,475.
Application 17/860,475 is a division of application No. 16/743,257, filed on Jan. 15, 2020, granted, now 11,693,662.
Application 16/743,257 is a continuation in part of application No. 15/970,915, filed on May 4, 2018, granted, now 11,294,851, issued on Apr. 5, 2022.
Claims priority of provisional application 62/883,967, filed on Aug. 7, 2019.
Prior Publication US 2022/0360428 A1, Nov. 10, 2022
Int. Cl. G06F 17/16 (2006.01); G06F 7/48 (2006.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 17/14 (2006.01)
CPC G06F 9/3812 (2013.01) [G06F 7/4806 (2013.01); G06F 8/4436 (2013.01); G06F 17/142 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method for configuring a reduced instruction set computer (RISC) processor architecture to execute a fully homomorphic encryption (FHE) logic gate as a streaming topology, wherein the RISC processor architecture includes a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary processing core having an associated node wrapper, the associated node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:
parsing sequential FHE logic gate code;
transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions;
creating the associated node wrapper around each code module; and
configuring at least one of the primary processing cores to implement a logic element equivalent of each element in a manner which operates in a streaming mode wherein data streams out of the corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.