US 12,293,187 B2
Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
Douglas Vanesko, Dallas, TX (US); and Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 30, 2023, as Appl. No. 18/524,942.
Application 18/524,942 is a continuation of application No. 17/399,801, filed on Aug. 11, 2021, granted, now 11,861,366.
Prior Publication US 2024/0111538 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/325 (2013.01) [G06F 9/3867 (2013.01); G06F 9/30065 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying a nested loop in a set of instructions;
configuring a first initiation interval of a first processing element of a set of interconnected processing elements to a first value and a second initiation interval of a second processing element of the set of interconnected processing elements to a second value, the second value a multiple of the first value, the first and second initiation intervals specifying a number of consecutive instructions allowed within a processing pipeline of each respective processing element;
assigning instructions of an inner loop of the nested loop to the first processing element and instructions of an outer loop of the nested loop to the second processing element; and
causing execution of the set of instructions by the first and second processing elements, the causing execution comprising encoding an indication of the configured first initiation interval and second initiation interval and the assignment of instructions into machine code representing the set of instructions or into metadata included along with the machine code.