| CPC G06F 9/30145 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01)] | 21 Claims |

|
1. An apparatus comprising:
circuitry to receive an instruction, the instruction to identify a first two-dimensional source tile that is to be stored in memory and a second two-dimensional source tile that is to be stored in the memory; and
execution circuitry to perform operations corresponding to the instruction, including to:
determine that an indicator indicates that a pair of matrices are to be loaded; and
load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded, wherein the execution circuitry is to load every element of the first two-dimensional source tile into the first two-dimensional destination tile, and load every element of the second two-dimensional source tile into the second two-dimensional destination tile.
|