US 12,293,141 B2
Integrated circuit stack verification method and system for performing the same
Feng Wei Kuo, Hsinchu (TW); Shuo-Mao Chen, Hsinchu (TW); Chin-Yuan Huang, Hsinchu (TW); Kai-Yun Lin, Hsinchu (TW); Ho-Hsiang Chen, Hsinchu (TW); and Chewn-Pu Jou, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,593.
Application 18/323,593 is a continuation of application No. 17/319,687, filed on May 13, 2021, granted, now 11,675,957.
Application 17/319,687 is a continuation of application No. 15/921,040, filed on Mar. 14, 2018, granted, now 11,023,647, issued on Jun. 1, 2021.
Application 15/921,040 is a continuation of application No. 14/621,054, filed on Feb. 12, 2015, granted, now 9,922,160, issued on Mar. 20, 2018.
Prior Publication US 2023/0297759 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); H01L 23/544 (2006.01); H01L 25/07 (2006.01)
CPC G06F 30/398 (2020.01) [H01L 23/544 (2013.01); H01L 25/07 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of verifying an integrated circuit stack, the method comprising:
adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate;
converting the first dummy layer location to the connecting substrate;
adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad; and
performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.