| CPC G06F 30/392 (2020.01) [G06N 10/40 (2022.01); G06F 2119/08 (2020.01)] | 20 Claims |

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1. A computer-implemented method comprising:
performing, by a system operatively coupled to a processor, analysis of a first design representation of a first layout of a first quantum chip that is to be connected to a second quantum chip to form a three-dimensional quantum chip, wherein performing the analysis comprises simulating the first design representation of the first quantum chip based on the first layout to extract quantum values of the first quantum chip; and
modifying, by the system, a second design representation of a second layout of the second quantum chip based on the analysis of the first design representation of the first layout of the first quantum chip to optimize the three-dimensional quantum chip according to a defined criterion associated with performances of the first quantum chip and the second quantum chip, wherein the modifying the second layout of the second quantum chip comprises simulating the second design representation of the second quantum chip based on the second layout to extract quantum values of the second quantum chip.
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