US 12,293,139 B1
Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory
Olivier Coudert, Sunnyvale, CA (US); Tien-Chien Lee, Sunnyvale, CA (US); Songra Pan, Sunnyvale, CA (US); and Suman Nandan, Milpitas, CA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by SYNOPSYS, INC., Sunnyvale, CA (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,571.
Claims priority of provisional application 63/228,355, filed on Aug. 2, 2021.
Int. Cl. G06F 30/31 (2020.01); G06F 30/33 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/31 (2020.01) [G06F 30/33 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit;
computing a plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph, wherein each SWCC of the plurality of SWCCs corresponds to a weakly connected component (WCC) of the reduced graph with a size less than or equal to a memory limit, and wherein each LWCC of the plurality of LWCCs corresponds to a WCC of the reduced graph with a size greater than the memory limit;
generating a first plurality of balanced subgraphs based on the plurality of SWCCs; and
generating a second plurality of balanced subgraphs based on the plurality of LWCCs, wherein each balanced subgraph of the first and second plurality of balanced subgraphs are configured to be simulated using a simulator with a processing capacity less than or equal to the memory limit.