US 12,293,108 B2
3D memory circuit
Javier A. DeLaCruz, San Jose, CA (US); and David E. Fisch, Corrales, NM (US)
Assigned to Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed on Jan. 23, 2023, as Appl. No. 18/100,110.
Application 18/100,110 is a continuation of application No. 17/098,299, filed on Nov. 13, 2020, granted, now 11,599,299.
Claims priority of provisional application 62/937,749, filed on Nov. 19, 2019.
Prior Publication US 2023/0376234 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/08 (2006.01); G06F 3/06 (2006.01); G11C 5/02 (2006.01); G11C 8/14 (2006.01); G11C 11/408 (2006.01); H01L 25/065 (2023.01); G11C 7/10 (2006.01); G11C 13/00 (2006.01); G11C 16/08 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G11C 5/025 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 11/408 (2013.01); H01L 25/0657 (2013.01); G11C 7/1006 (2013.01); G11C 13/0023 (2013.01); G11C 16/08 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an integrated circuit (IC) die stack comprising a first die and a plurality of second die, wherein:
the first die comprises global data lines, global input/output (I/O) circuits, and processing cores;
each of the plurality of second die comprises:
memory blocks,
local data lines connected to the memory blocks,
an addressing circuit, and
a local input/output (I/O) circuit;
an active side of the first die is directly bonded to a topmost second die of the plurality of second die;
the local data lines of the topmost second die of the plurality of second die are communicatively coupled to the global data lines of the first die;
the processing cores are capable of receiving, through the global I/O circuits, data from the memory blocks and providing, through the global I/O circuits, data to the memory blocks;
each addressing circuit is capable of activating different memory blocks of the respective second die; and
each local input/output (I/O) circuit is capable of writing/reading data to the respective activated memory blocks.