US 12,293,107 B2
Method and apparatus to perform a multiple bit column read using a single bit per column memory accessible by row and/or by column
Chetan Chauhan, Folsom, CA (US); Sourabh Dongaonkar, Portland, OR (US); and Jawad B. Khan, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 5, 2021, as Appl. No. 17/519,799.
Prior Publication US 2022/0057961 A1, Feb. 24, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
R non-volatile memory dies, each non-volatile memory die comprising a cross-point memory array having rows and columns of memory cells to store an array of bits, each column to store one-bit of a R-bit entry in an M-bit logical column; and
circuitry to cause storage of R-bit entries in the M-bit logical column in the cross-point memory array diagonally across a partition having Q rows and Q columns in the cross-point memory array with a first R-bit entry in the M-bit logical column stored across the R non-volatile memory dies, each bit of the first R-bit entry stored at a same physical row address and physical column address in one of the R non-volatile memory dies.