US 12,293,089 B2
Semiconductor memory device and method of operating the same including detrap operation for lowering memory cell threshold voltages
Dong Jae Jung, Icheon-si (KR); Jae Woong Kim, Icheon-si (KR); and Shin Won Seo, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 8, 2022, as Appl. No. 18/077,727.
Claims priority of application No. 10-2022-0080003 (KR), filed on Jun. 29, 2022.
Prior Publication US 2024/0004558 A1, Jan. 4, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory block including a plurality of pages;
a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to at least one selected memory cell, among a plurality of bit lines of the memory block, during a detrap operation on the at least one selected memory cell included in a page selected from among the plurality of pages, and apply a second bit line voltage having a potential lower than a potential of the first bit line voltage to an unselected bit line, among the plurality of bit lines, during the detrap operation;
a voltage generation circuit configured to generate a first set voltage and a second set voltage during the detrap operation; and
an address decoder configured to apply the first set voltage to a selected word line corresponding to the selected page and apply the second set voltage having a potential higher than a potential of the first set voltage to unselected word lines, during the detrap operation,
wherein the first bit line voltage has a ground voltage level and the second bit line voltage has a negative potential.