| CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |

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1. A memory device comprising:
plural memory cells, each of the plural memory cells capable of storing multi-bit data corresponding to an erase state and plural program states; and
control circuitry configured to divide plural program loops, which are performed to store the multi-bit data in the plural memory cells, into plural program groups and apply different program pulses, which correspond to each of the plural program groups, to the plural memory cells, wherein the control circuitry is configured to perform the plural program loops in one or more odd numbered program loops and one or more even numbered program loops.
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