| CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |
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1. An apparatus, comprising:
a memory device including a plurality of memory arrays;
a memory controller configured to control the memory device, the memory controller having a read queue, a write queue, and an address match circuit; and
a data output circuit,
wherein the data output circuit is directly connected to both the memory device and the memory controller,
wherein the memory controller is configured to receive a read request, search the write queue for a write address that matches a read address of the read request, and send data associated with the write address from the write queue to the data output circuit without accessing the memory device when the write address matches the read address, the write address that matches the read address being a target address, and
wherein, when there is the target address in the write queue, the data output circuit is configured to output the data associated with the target address, received from the write queue, to an external device in response to a read pulse that is enabled by the read request, and
wherein, when the target write address is absent in the write queue, the data output circuit is configured to output data associated with the read address, received from the memory device, to the external device in response to the read pulse.
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