US 12,293,085 B2
Data storage device and method for improving asynchronous independent plane read (AIPR) utilization
Pradeep Seetaram Hegde, Uttar Kannada (IN); Ramanathan Muthiah, Bangalore (IN); Nagaraj Dandigenahalli Rudrappa, Davangere (IN); and Vimal Kumar Jain, Bangalore (IN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/225,771.
Claims priority of provisional application 63/521,914, filed on Jun. 20, 2023.
Prior Publication US 2024/0427494 A1, Dec. 26, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 11/16 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1612 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7205 (2013.01)] 19 Claims
OG exemplary drawing
 
1. In a data storage device comprising a memory comprising a plurality of memory dies and asynchronous independent plane read (AIPR) circuitry, a method comprising:
receiving a plurality of memory bit-error rate (BER) check requests from a respective plurality of garbage collection modules in the data storage device, wherein the plurality of memory BER check requests are generated by the plurality of garbage collection modules at different times; and
instead of sending the plurality of memory BER check requests to the memory to execute sequentially as the plurality of memory BER check requests are received at the different times:
consolidating the plurality of memory BER check requests such that BER check requests from respective garbage collection modules are consolidated for respective different planes of the plurality of memory dies; and
sending the consolidated plurality of memory BER check requests to the AIPR circuitry to execute the BER check requests for the garbage collection modules in parallel across the respective planes of the plurality of memory dies.