US 12,293,081 B2
Method and system for generating memory maps
Raghu Vamsi Krishna Talanki, Bengaluru (IN); Archita Khare, Bengaluru (IN); Eldho P. Mathew, Bengaluru (IN); Jin In So, Bengaluru (IN); Jong-Geon Lee, Suwon-si (KR); Venkata Ravi Shankar Jonnalagadda, Suwon-si (KR); and Vishnu Charan Thummala, Bengaluru (IN)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 2, 2023, as Appl. No. 18/310,741.
Claims priority of application No. 202341014161 (IN), filed on Mar. 2, 2023.
Prior Publication US 2024/0295963 A1, Sep. 5, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of generating memory maps, the method comprising:
detecting, by a computing system, at least one of a Dual In-Line Memory Modules (DIMM) and one or more Dynamic Random Access Memory (DRAM) chips associated with the computing system, wherein one or more accelerators are configured in at least one of the DIMM and the one or more DRAM chips;
determining, by the computing system, accelerator information for each of the one or more accelerators based on flags stored in reserved bytes of at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of the DIMM and one or more DRAM chips, the accelerator information providing information regarding the one or more accelerators present in the at least one of the DIMM and the one or more DRAM chip;
generating, by the computing system, a unique memory map for each of the one or more accelerators based on the accelerator information of the corresponding one or more accelerators.