| CPC G06F 3/061 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |
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1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
initiating an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device;
causing, during a first stage of the erase operation, one or more erase pulses of the erase operation to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently, wherein the one or more erase pulses cause a source voltage associated with each of the first memory block and the second memory block to be ramped to an erase voltage level;
causing, during the first stage of the erase operation, one or more first erase verify sub-operations of the erase operation to be performed to verify a first threshold voltage distribution level associated with the first memory block is less than a first erase verify threshold voltage level;
causing, during the first stage of the erase operation, one or more second erase verify sub-operations of the erase operation to be performed to verify a second threshold voltage distribution level associated with the second memory block is less than the first erase verify threshold voltage level; and
in response to completion of the first stage of the erase operation, causing, during a second stage of the erase operation, execution of one or more erase/program verify sub-operations to concurrently verify the first memory block and the second memory block are erased.
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