US 12,292,843 B2
Transferring data to a memory device based on importance
Robert Bielby, Placerville, CA (US); and Junichi Sato, Yokohama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 19, 2023, as Appl. No. 18/470,144.
Claims priority of provisional application 63/408,371, filed on Sep. 20, 2022.
Prior Publication US 2024/0095200 A1, Mar. 21, 2024
Int. Cl. G06F 13/18 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/18 (2013.01) [G06F 13/1626 (2013.01); G06F 13/4221 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
a first memory device;
a second memory device having a lower write latency than the first memory device;
a solid state drive; and
a controller coupled to the first memory device and the second memory device via a compute express link (CXL) interface;
wherein the controller is configured to:
receive data comprising a hierarchy of importance levels for different data types and store the data comprising the hierarchy of importance levels for the different data types, wherein the controller is configured to receive the data comprising the hierarchy of importance levels for the different data types prior to the solid state drive being in use by a vehicle in which it is installed or will be installed;
assign an importance level to a write request based on:
data associated with the write request;
the hierarchy of importance levels for the different data types; and
the second memory device having the lower write latency than the first memory device;
transfer the data to the first memory device in response to the assigned importance level having a first value; and
transfer the data to the second memory device in response to the assigned importance level having a second value.