CPC G06F 12/1458 (2013.01) [G06F 12/1009 (2013.01); G06F 12/1425 (2013.01); G06F 12/145 (2013.01); G06F 2212/1052 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
a memory protection cache to store memory protection information while a first device and a non-host memory device are coupled to each other via a network switch, and while the first device and the non-host memory device are each coupled, via the network switch, to a root complex of a host, wherein the non-host memory device is to comprise the apparatus; and
circuitry coupled to the memory protection cache, the circuitry to:
synchronize the memory protection information stored at the memory protection cache with a memory protection unit of the root complex, wherein the memory protection information is to identify memory access permissions at a page-level granularity;
perform one or more memory protection checks on a translated peer-to-peer memory access request based on the memory protection information stored in the memory protection cache, wherein the one or more memory protection checks are to determine a memory access permission of the first device; and
block or allow the translated peer-to-peer memory access request based on the one or more memory protection checks;
wherein:
the apparatus is to receive the translated peer-to-peer memory access request from the first device via the network switch;
the translated peer-to-peer memory access request comprises a host physical address to be targeted; and
a communication of the translated peer-to-peer memory access request from the first device to the apparatus is to bypass the root complex of the host.
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