US 12,292,836 B2
Cache synchronization for chiplet accelerators
Preyesh Dalmia, Madison, WI (US); Rajesh Shashi Kumar, Madison, WI (US); and Matthew D. Sinclair, Middleton, WI (US)
Filed by Wisconsin Alumni Research Foundation, Madison, WI (US)
Filed on Mar. 22, 2023, as Appl. No. 18/188,209.
Prior Publication US 2024/0320158 A1, Sep. 26, 2024
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0815 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0815 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of operating a computer architecture having:
a set of computational chiplets providing integrated circuitry on physically separated substrates, each computational chiplet providing a cache;
an interposer providing a communication pathway between the chiplets on a substrate physically separate from the substrates of the chiplets;
a global command processor for receiving commands from a host processor external to the interposer indicating: a given computational chiplet type, a given computational chiplet kernel providing instructions to be executed by a given computational chiplet type, and further receiving information identifying a given operand array for the given kernel; the global command processor including a chiplet coherency table linking previously executed kernels to associated and identified operand arrays, the method operating to:
(1) direct the kernel to a given chiplet;
(2) determine whether any chiplets other than the given chiplet have copies of an operand array identified to the given chiplet; and
(3) elide a flushing of the caches of the other chiplets when there are no copies of the given operand array.