| CPC G06F 12/0862 (2013.01) [G06F 2212/602 (2013.01)] | 18 Claims |
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1. An apparatus, comprising:
associating circuitry configured to associate an indirect prefetch condition with a first memory access request, for accessing data at a first address in a memory system, in response to anticipating, based on hint information received from associated processing circuitry, that the data to be accessed at the first address in response to the first memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request;
address generating circuitry, responsive to association of the indirect prefetch condition with the first memory access request and determination that the address indicating data associated with the first address is available in an associated cache, to generate a second address using the address indicating data;
prefetch request issuing circuitry configured to issue prefetch memory access requests to seek to make data available in the associated cache in anticipation of access to said data being requested by the associated processing circuitry;
wherein the prefetch request issuing circuitry, responsive to the address generating circuitry generating the second address, is arranged to issue a prefetch memory access request to seek to make data at the second address available in the associated cache; and
the apparatus comprises the associated processing circuitry configured to perform data processing operations in response to instructions, wherein
the associated processing circuitry is configured to transmit the hint information to the associating circuitry in respect of a given demand memory access request in response to detecting one or more instructions indicating that data returned in response to the given demand memory access request is to be used to generate an address for a subsequent demand memory access request.
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