CPC G06F 12/0828 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 2212/621 (2013.01)] | 20 Claims |
1. A method comprising:
receiving a first memory transaction request for a first memory line from a first processor core of processor cores of a processing system, wherein the processor cores comprise a second processor core and a third processor core;
determining, by a memory coherency manager circuit, that the second processor core comprises the first memory line in a shared state;
selecting, by the memory coherency manager circuit, the second processor core to provide the first memory line to the first processor core based on index bits of a second memory transaction request received from the second processor core differing from index bits of the first memory transaction request, and a first number of coherency transactions between the second processor core and the memory coherency manager circuit and a second number of coherency transactions between the third processor core and the memory coherency manager circuit; and
communicating data of the first memory line from the second processor core to the first processor core based on selecting the second processor core.
|