US 12,292,832 B2
Memory coherence protocol for communicating data associated with a shared state between processor cores
Karthik Thucanakkenpalayam Sundararajan, Fremont, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 27, 2022, as Appl. No. 17/974,881.
Prior Publication US 2024/0143506 A1, May 2, 2024
Int. Cl. G06F 12/0817 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0828 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a first memory transaction request for a first memory line from a first processor core of processor cores of a processing system, wherein the processor cores comprise a second processor core and a third processor core;
determining, by a memory coherency manager circuit, that the second processor core comprises the first memory line in a shared state;
selecting, by the memory coherency manager circuit, the second processor core to provide the first memory line to the first processor core based on index bits of a second memory transaction request received from the second processor core differing from index bits of the first memory transaction request, and a first number of coherency transactions between the second processor core and the memory coherency manager circuit and a second number of coherency transactions between the third processor core and the memory coherency manager circuit; and
communicating data of the first memory line from the second processor core to the first processor core based on selecting the second processor core.